Computer

ABSTRACT

A computer is disclosed wherein the machine language thereof is a particular formal system, i.e., the &#39;&#39;&#39;&#39;calculus of lambda conversion.&#39;&#39;&#39;&#39; Such machine language is the language of the &#39;&#39;&#39;&#39;well-formed&#39;&#39;&#39;&#39; formulas of the aforementioned lambda calculus whereby the theoretical properties of the lambda calculus are implemented in the computer. Consequently, the computer is capable of computing all computable functions with time and space being the only limitations. The nerve center of the system is termed a tablet which in one implementation may essentially consist of an array of high-speed registers, each one large enough to hold a primitive term together with its designator. The nodes of a tree given by some formula corresponds to rows in the tablet and the branches extending from the nodes correspond to columns in the tablet. In one embodiment, the tablet has three columns for the branches and can have a fourth column which holds the tree addresses of the nodes. Associative techniques permit access to a row upon a match with the contents of the data or designator fields of one or more columns. The basic unit of information consists of the contents of a complete row of the tablet, such unit being termed a &#39;&#39;&#39;&#39;message.&#39;&#39;&#39;&#39; The tablet, functioning as a central communication device, communicates with functional units, memory units, and input-output units, the latter issuing and accepting messages, or merging them with existing ones when the units obtain access to the tablet. The invention contemplates either the accessing by the units of the whole tablet, one after another in a fixed sequence, or the accessing by each unit of only a subset of the tablet, all units simultaneously accessing discrete subsets respectively. In order to render all messages available to all units, all of the messages are circulated, i.e., shifted through the whole tablet.

United States Patent Berkling I Feb. 29, 1972 [54] COMPUTER [72]Inventor: Klaus Juergen Berkllng, Granite Springs,

[73] Assignee: International Business Machines Corporation, Armonk, N.Y.

[22] Filed: Sept. 24, 1969 [21] Appl. No.: 860,473

[52] US. Cl. ..340/172.5 [51] Int. [58] Field of [56] References CitedOTH ER PUBLICATIONS Schaffner, The Circulating Page Loose System, A NewSolution for Data Processing, Research Report No. 15, Published bySmithsonian Astrophysical Observatory, Dec. I966 Primary Examiner-RaulfeB. Zache Assistant Examiner-Ronald F. Chapuran Attorney-Hamlin and.Iancin and Isidore Match [57] ABSTRACT of the well-formed formulas ofthe aforementioned lambda calculus whereby the theoretical properties ofthe lambda calculus are implemented in the computer. Consequently, thecomputer is capable of computing all computable functions with time andspace being the only limitations. The nerve center of the system istermed a tablet which in one implementation may essentially consist ofan array of high-speed registers, each one large enough to hold aprimitive term together with its designator. The nodes of a tree givenby some formula corresponds to rows in the tablet and the branchesextending from the nodes correspond to columns in the tablet. In oneembodiment, the tablet has three columns for the branches and can have afourth column which holds the tree addresses of the nodes. Associativetechniques permit access to a row upon a match with the contents of thedata or designator fields of one or more columnsf'l'he basic unit ofinformation consists of the contents of a complete row of the tablet,such unit being termed a message." The tablet, functioning as a centralcommunication device, communicates with functional units, memory units,and input-output units, the latter issuing and accepting messages, ormerging them with existing ones when the units obtain access to thetablet. The invention contemplates either the accessing by the units ofthe whole tablet, one after another in a fixed sequence, or theaccessing by each unit of only a subset of the tablet, all unitssimultaneously accessing discrete subsets respectively. In order torender all messages available to all units, all of the messages arecirculated, i.c., shifted through the whole tablet.

14 Claims, 133 Drawing Figures IIIPUT STORE "D- 5T0li IP UP BETAMINI-LOGIC lIlITII-LOGIC OUTPUT UIII'I' UNIT 1 IIIIIT mm II T IlIIlTIIIIIT I UIIIT ll IIIIIY LINEAR MEMORY PATENTEDFEBZH 1912 3,646,523

SHEET 0311183 FIG. 4 FIG. 5

STRUCTURES TREE STRUCTURE FUNCTIONS 0N U RELATIONS 0N U LINEAR STRUCTURENATURAL NUMBERS (((D-EHCHAH-BH) SHH)"HH/S(O')"O'1,0'N SUU-m'O' cr creTFIG. 6 FIG. 7

TREE ADDRESSING VERSUS MACHINE LANGUAGE MAPPING OF TREE STRUCTURESSYNTAX:

FORWD' (ADDRESS t t P1 W 1 1,1

P4 t t,t,t P3 t {PRIMITIVE 151111} 5 En SEMANTTCS1 ))(q .m)p)) {Pl,.,,.,P11} DATA 1111111 TFO ....O' m=MEMORY SIZE 3 'rnloq m 511s M2 5115PAIENTEDFEBZS I972 3.646523 SHEET mm 83 FIG. 8

SYSTEM ARCHITECTURE TABLET= )Lv 25 M "X EXJZ NA MX L 3 )5 2,, 5

x123 A if I I I ml 1 l I FUNCTIONAL UNITS FIG. 9 FIG. 10

I SA'ACCEPTANCE STATE,

SE-ERROR STATE STATE DIAGRAM FOR neVf'lxkeVt S, SUCCESSORFUNCTION=V1'xVf*VfST(S,l\,n)-nk Ta (TRTT '(P.T1)UNDEF|NE0T0= =UNDEFINEDPAIENTEDrwzsmrz 3,646,523

SHEET CBUF 83 FIG. 15

CH RAC 2L E AINPUIER pusuooww I T J STACK I I I I L J J N0 U DPERATIONPRIME I PRIME I H v I4 I W I l I W I I I I I I I l I I I l I I I L L I iJ L L 5 S L J; J

TABLET COMMUNICATION REGISTERS PAIENIEDFEB29 I972 SHEET CSUF 83PAIENIEDFEBZB m2 3,646,523

SHEET 10 0F 83 FIG. 17C

PATENTEUFEBZS I972 3.646.523

sum 11 (1F 83 FIG. 17D

PAIENTEnmszs :912 3,646,523

SHEET 13 [1F 83 FIG.17F

READ COMPLETE COMPLETE PATENTEDFEBZSIBTZ 3,646,523

SHEET 150? 83 ASSOCIATIVE MEMORY CONTROL F I 19A wRITE A SELECT) F.

READ SELJECT 162" l I A 446 A FIF IL I 5 CA3 A Z A A Z v A j READ sE EcTFF J T *1 0 IIRITE A A 2 TIcIsII A READ SELIECT TI T I F. I 0 WRITE cA-IA A A SELECT) M 1L M W q A l READ W VVVV q SELECT) T T FF I52 A J I 065-1 A A I Y WRITE REIII) I IRITE PAHZNTEDFEBZSIQYZ 3.646.523

SHEET 15 [1F 83 FIG. 19B ASSOCIATIVE DATA MEMORY PLANE WORD 1 WORD1 WORD1 BiT#1 BIT#2 B|T#161 worm 2 WORD 2 WORD 2 BIT#I BIT# 2 B1T# 161 WORD :1WORD 3 WORD a BIT #1 BIT#2 a11#1s1 WORD 4 wono 4 wono 4 B11 1 1111111 2BIT#16I 1 w 111 I i (DATA 01-2 PULSE 13 1111 11111 MJ 10 1111s 11111 1010011 f 011-2 1 11151 15 11111111 1011 1111 11 51101 111 s111c11n 111115101001 FOR INPUT MESSAGE FAIENIEUFEBZSIBTZ 3,646,523

QHEET 17UF 83 ASSOCIATIVE MEMORY VACANCY BIT STORAGE ELEMENT (BIT 1INITIAL RESET wans SELECT 0 FIG. 21 fiw MISMMEL 4Q;Assoc|m 7 1 0 READsum W sum 3610 /3 ASSOCIATIVE M EMORY STORAGE ELEMENT(B|T 2161) w WRITESELECT ASSOCIATE

1. A computer comprising: input channel means for forming the inputentering into said computer into meaningful tokens, said tokenscomprising three portions, viz, a descriptor for indicating the class ofthe token, the body, and a delimiter for indicating the end of thetoken, the classes of said tokens including integers, truth values,function constants which include functions from numbers to numbers,functions from number to truth values and functions from truth values totruth values, output device names, variable names, binding variablesdefinition labels, defined expression names, conditional indicators,leFt parenthesis, and right parenthesis; a plurality of functional unitsfor carrying out data-processing operations; central communication meansfor receiving from and providing information to said functional units inaccordance with the calculus of lambda conversion; and linear memorymeans for containing a copy of a program throughout its execution.
 2. Acomputer comprising: data-processing means for constituting the calculusof lambda conversion as the machine language of said computer, said lastnames means comprising: means for receiving input into said computercharacter by character in the form of fully parenthesized expressions,said expressions respectively representing programs; input means forforming said character-by-character input into meaningful tokens, eachof said tokens including a descriptor portion for indicating the classof token, a body and a delimiter for indicating the end of the token;linear memory means for containing said tokens in said program form;central communication means; storage means for controlling the storingand fetching of data from said memory; node-assembling means forbuilding said parenthesized expressions into program trees in saidcentral communication means, said trees respectively comprisingdiffering level nodes followed by n successor functions; means forevaluating variable nodes in said trees; said central communicationmeans communicating with said input, storage, node assembling andvariable more evaluating means by receiving messages therefrom andproviding messages therefor; and second means for effecting theprocessing of data in said first means in accordance with said calculus.3. A computer as defined in claim 2 wherein said data-processing meansfurther includes: arithmetic logic means for carrying out arithmetic andlogical operations in said computer; and output means for providing theresults of the processing of data in said computer.
 4. A computercomprising: data-processing means for constituting the calculus oflambda conversion as the machine language of said computer, said lastnamed means comprising: central communication means; input means forreceiving balanced parenthesis formulas character by character and forreassembling said characters into meaningful strings; linear memorymeans for containing the characters of said formulas in respectiveconsecutive locations therein, said characters being placed in saidmemory to form said formulas; said input means being operative to placemessages in said central communication means; storage means foreffecting the storage of information in said memory, said storage meansbeing operative to place messages in and receive messages from saidcentral communication means relative to the storing and fetching ofinformation from said memory; node-assembling means for assembling aformula as a program tree comprising successive level nodes in saidcentral communication means, said node-assembling means being operativeto place messages in and receive messages from said centralcommunication means; beta conversion means for effecting a betaconversion of the elements of said trees in accordance with the betaconversion rule of said calculus, said beta conversion means beingoperative to place messages in and receive messages from said centralcommunication means; and ''''UP'''' means for effecting the sending upof information to said nodes, said last-named means being operative toplace messages in and receive messages from said central communicationsmeans.
 5. A computer as defined in claim 4 wherein said data-processingmeans further includes: arithmetic and logic means for carrying outarithmetic and logical operations, said last named means being operativeto place messages in and receive messages from said centralcommunication means; and output means for effecting the output of theresults which eNsue from the processing of said respective expressions,said output means being operative to place messages in and receivemessages from said central communication means.
 6. A computer as definedin claim 5 wherein the input hereinto is a formula of a balancedparenthesis form, said formula comprising strings of symbolsrespectively forming logical groups which are tokens, each of saidtokens comprising a descriptor for indicating the type of token, a tokenbody and a delimiter for indicating the end of the token; saiddescriptors including integers floating-point numbers, numbers of chosennumerical systems, truth values, the bodies of tokens having truth valuedescripters being true (T) or false (F), function constants comprisingfunctions from numbers to numbers, functions from numbers to truthvalue, and functions from truth values to truth values, output devicenames, variable names, binding variable, definition labels, definedexpression names, conditioned indicators, left parenthesis, and rightparenthesis.
 7. A computer as defined in claim 6 wherein said centralcommunication means is an associative memory comprising an array ofregisters, each of said registers having a length of one word, the nodesof a tree given by a formula corresponding to rows in said centralcommunication means, the branches emanating from the nodes correspondingto columns in the central communicating means, a tablet row forreceiving a tablet entry comprising a first plus n following words toform an n-ary tree, said first word holding the node label of the treenode the entry is for, said n words holding tokens under said node.
 8. Acomputer as defined in claim 7 wherein said input means comprises: afirst register for receiving an input token character by character andfor containing the address in linear memory to which said token is togo: a second register for receiving tokens other than left parenthesesand conditional indicators, and their respective memory address fromsaid first register, a token receiving a prime in said card secondregister provided that the next token is a right parenthesis; a thirdregister for forming a central communication means entry; a pushdownstack for holding left parenthesis and conditional indicator tokensuntil the location of the nonright parenthesis token following therematching right parenthesis is known; a fourth register for receivingwords from and providing words to said pushdown stack; and a fifthregister for holding the information for the last left parenthesis orconditional indicator for which the matching right parenthesis is found.9. A computer as defined in claim 7 wherein said node assembler meanscomprises means responsive to a message therefor in said centralcommunication means which includes a node label, a blank or backpointer, a node assembler operation code, a location in said linearmemory and a token retrieved from a chosen location in said linearmemory for placing messages in said central communication means inresponse to the combination of the code assembler operation code and thetoken in said message for said node assembler means, said messagesplaced by said node assembler means in said central communication beinginserted into rows of said central communication means.
 10. A computeras defined in claim 7 wherein said beta conversion means includes meansfor scanning said central communications means for variable nodes andmeans for looking up the value of a variable through back pointers. 11.A computer as defined in claim 7 wherein said ''''UP'''' means includesmeans to ascertain the tree position of said nodes in a program formula;and means for checking as to whether the value expression for a variableevaluates to a complex expression.
 12. A computer comprising: anassociative memory; for handling programs and data in tree form, toeffect the traversal, transformation and copying of trees whereby saidtrees are caused to collapse and grow; means for effecting generalsubstitution procedures such that end points of branches of trees arereplaced by trees recursively, in accordance with the lambda calculus,whereby subtrees are designated to be constituted for said end points,using variables in accordance with said lambda calculus. means forgenerating linear strings of symbols from trees; means for generatingtrees from linear input strings; means for storing a tree whereby treestructures are intrinsic to the addresses of nodes, said associativememory holding said tree addresses and for causing coordinate memoryaddresses to be interpreted as tree addresses; shift register means; andmeans to compute predecessor and successor functions on said treeaddresses with said shift register means.
 13. A central communicationmeans for a computer comprising; a matrix of registers, each of saidregisters being capable of containing n words, each of said wordscomprising m bytes; said registers being arranged in k conceptuallyhorizontal planes, each of said planes comprising a like amount of saidregisters, said registers defining the rows of said planes,corresponding bits in said registers defining the columns in saidplanes, corresponding registers in each of said k planes beingconceptually vertically disposed in registration whereby each row ofsaid matrix is a conceptually vertical planar array comprising kregisters; and means for effecting the transferring of informationthrough said matrix from register to register in respective oppositedirections in adjacent ones of said planes whereby information iscirculated through said matrix in a serpentine manner to effectivelyprovide a multiple rank shift register.
 14. A central communicationmeans as defined in claim 13 and further including associative circuitmeans for enabling each of said conceptually vertical planar arrays ofregisters to function as respective associative memories.